Circuit testing method and apparatus

ABSTRACT

Method and apparatus for testing complexes of circuits, such as printed circuit boards and the like, for continuity of desired circuits and absence of short circuiting are provided. A circuit board having a plurality of possible circuit nodes has each node scanned sequentially by a step switch or the like. As each node is scanned in one embodiment, all lower order nodes are electrically interconnected, and means are provided for sensing closed circuit and open circuit signals between the scanned node and interconnected nodes. Logic is provided for &#39;&#39;&#39;&#39;rejecting&#39;&#39;&#39;&#39; a board if both the closed circuit sensing and open circuit sensing are either within or without acceptable limits and for &#39;&#39;&#39;&#39;accepting&#39;&#39;&#39;&#39; a board if either is within the limits when the other is without. Signals representative of the presence or absence of a circuit for each node as scanned is applied to a cyclic shift register having fewer bits than the number of circuit nodes. After all the nodes have been scanned, the final word in the cyclic shift register is compared with an input word for providing an output signal indicative of identity or lack of identity of the measured word and the comparison word. By sensing continuity between each circuit node sequentially while all lower order nodes are interconnected the lowest order node in each continuous circuit is identified, and an acceptable circuit can be distinguished from an unacceptable circuit without exploring each circuit path separately, thereby greatly reducing the circuit testing time.

7 United States Patent 3,763,430

Terrey Oct. 2, 1973 CIRCUIT TESTING METHOD AND APPARATUS [57] ABSTRACTnto Charles H. Terrey, Covina, Calif. Method and apparatus for testingcomplexes of cir- [73] Assignee: Burroughs Corporation Detroit cuits,such as printed circuit boards and the like, for

Mich continuity of desired circuits and absence of short circuiting areprovided. A circuit board having a plurality Filed: J 1972 of possiblecircuit nodes has each node scanned se- [ZI] Appv NOJ 217,859 quentiallyby a step switch or the like. As each node is scanned in one embodiment,all lower order nodes are Related U.S. Application Data electricallyinterconnected, and means are provided for [63] continuation f Set No.17,443. March 9, 1970 sensing closed circuit and open circuit signalsbetween abandoned. the scanned node and interconnected nodes. Logic isprovided for rejecting a board if both the closed cir- [52] U.S. Cl.324/73 R, 324/51 cuit sensing and open circuit sensing are either within[51] Int. Cl G0lr 15/12 or without acceptable limits and for accepting a[58] Field of Search 314/51, 52, 66, 67, board if either is within thelimits when the other is 314/73 without. Signals representative of thepresence or absence of a circuit for each node as scanned is applied[56] References Cited to a cyclic shift register having fewer bits thanthe numn' STATES PATENTS ber of circuit nodes. After all the nodes havebeen 3,441,849 4/1969 Bennet 324 73 Scanned the final wmd the cyclicShift register is 3,471778 10/1969 Benn?t u 324/73 compared with aninput word for providing an output 3370232 2,1968 wickersham 324/73signal indicative of identity or lack of identity of the 3,492,57l1/1970 Deslar 324 73 measured Word and the Comparison WOIdy SensingOTHER PUBLICATIONS continuity between each circuit node sequentiallywhile all lower order nodes are interconnected the lowest order node ineach continuous circuit is identified, and an acceptable circuit can bedistinguished from an unacceptable circuit without exploring eachcircuit path separately, thereby greatly reducing the circuit TechnicalManual, Operation And Maintenance Back Plane Validation System, Pub. byDITMCO, pp. 1-1 to l-4, 2-1 to 2-17, 31 to 3-6, 4-l to 4-23, 5-1 to5-23, Appendix I, Appendix II.

. testing time. 1 Primary Examiner-Michael J. Lynch A!!0rney--Robert L.Parker et al. 24 Claims, 8 Drawing Figures ll PPEA/T w FJJ'L J 38 Wowr/imif'fif 1 frf- 3 7 57P1470Y w zj gg' :sw/ra/ 33 I I L J PATENTEDBBT 23.763.430

SHEET 10F 2 A TTOR/VE Y5 CIRCUIT TESTING METHOD AND APPARATUS This is acontinuation of my application Ser. No. 17,4l3, filed Mar. 9, 1970 nowabandoned.

BACKGROUND Many pieces of modern electronic equipment rely heavily onvery large scale printed circuit boards or panels having pinsinterconnected in complex patterns by conductors of various types. Suchboards are commonly used in computers and many other types of electronicequipment having complex circuitry. Such boards are fabricated withconductive paths, either in the form of circuits printed on the board orwiring between pins, prior to the installation of active circuitcomponents on the board. After the printed circuit board is prepared, orthe pin-type board is wired, it is desirable to check the circuits onthe board to verify that all desired circuits have been made, that is,there are no open circuits, and also to verify that no unintentionalcircuits have been made, that is, short circuits. On a circuit boardthere are usually many circuits that prior to installation of activecircuit components are not connected to the input and output leads ofthe board. There are, however, many points on the board to whichelectrical contact can be made, and these points can be considered ascircuit nodes. Thus, for example, in a wired board each of the pins towhich components are to be attached or sockets in which they are to beinserted provides a possible circuit node. On a printed circuit board,the circuit nodes are points at which circuit elements such astransistors, memory devices, resistors, connectors and the like aresubsequently connected.

After a board has been manufactured, it is desirable to check and makesure that each circuit node is correctly connected to each circuit nodeto which it is supposed to be connected, and it is also desirable toverify the absence of unintentional connections. Such faults in a wiredboard can occur if, for example, wires are not properly connected to apin to provide a good electrical contact, or if a wire is connected tothe wrong pin, or if two wires are accidentally shorted together, or ifa wire is broken. In a printed circuit board such faults can occur, forexample, due to lack of plating within a plated-through hole, or due tothe presence of a small conductive path between circuit paths due to ablemish in a photographic negative or a failure in an etching solution.It should be recognized that these are merely typical faults that mayoccur in a circuit board, and it is very difficult to identify sucherrors by manual inspection. Modern boards may involve hundreds or eventhousands of circuit nodes, and manual testing is prohibitive.

Circuit testing apparatus have therefore been developed for checking thepresence or absence of conductive paths between the several circuitnodes on a circuit board. The prior technique has been to check onecircuit node against each of the other circuit nodes in turn and thenindividually check each other circuit node against all other circuitnodes on the board to trace down each possible circuit path. The circuitpaths found in this manner are then compared with the desired circuitpaths to verify the acceptability of the board. Such apparatus issuitable when there are a limited number of possible circuit nodes;however, in modern boards with hundreds or thousands of circuit nodes,the time required to scan the entire board becomes prohibitive. Somescanning patterns have involved factorial increases of number of stepswith increasing number of pins, and the time is prohibitive inproduction processes where it is not uncommon to check hundreds ofboards per day. Thus, for example, even when the scanning is conductedat a rate in the order of megacycles per second, a matter of minutes maybe required to check out all the possible circuit paths on a large-scaleboard.

It is therefore desirable to provide a method and apparatus forverification of the circuits on a circuit board in a very short timeinterval.

BRIEF SUMMARY OF THE INVENTION Therefore, in practice of this inventionaccording to a preferred embodiment there is provided a circuit testingapparatus for testing a circuit having a plurality of nodes comprisingmeans for sequentially applying a signal to one test node after another,and at the same time interconnecting all lower order circuit nodes andmeans for sensing the signal on the set of interconnected nodes. Signalsindicative of the presence or absence of a circuit can be applied tomeans for generaling a number having fewer bits than the number ofcircuit nodes. Means may also be provided for comparing the shorternumber with a number representative of an acceptable circuit for passingor rejecting circuits under test. Multiple scans or different degrees ofdata compression can be employed for identifying unacceptable boardseven in presence of certain rather rare cir cuit faults.

DRAWINGS These and other features and advantages of the presentinvention will be appreciated as the same becomes better understood byreference to the following detailed description of a presently preferredembodiment when considered in connection with the accompanying drawingswherein:

FIG. 1 illustrates in block diagram a circuit testing apparatusconstructed according to principles of this invention;

FIG. 2 illustrates a typical acceptable circuit board;

FIG. 3 illustrates a board like that of FIG. 2 with an unintentionalopen circuit;

FIG. 4 illustrates a board like that of FIG. 2 with an unintentionalshort circuit;

FIG. 5 illustrates a board like that of FIG. 2 having desiredconnections inadvertently interchanged;

FIG. 6 illustrates a board like that of FIG. 2 with a different pair ofconnections inadvertently interchanged;

FIG. 7 illustrates a board like that of FIG. 2 having an open circuitand a short circuit; and

FIG. 8 illustrates in block form a fragment of circuit testing apparatusfor detecting certain circuit faults of the sort illustrated in FIGS. 3to 7.

DESCRIPTION FIG. 1 illustrates in block diagram'form a circuit testingapparatus constructed according to principles of this invention. In thispreferred embodiment, a circuit testing jig 21 is employed for makingelectrical connections to a circuit board such as that illustratedschematically in FIG. 2. The circuit test jig 21 is a conventional itempresently employed with circuit testing apparatus and merely provides afixture for holding the board and making electrical contact to selectedpoints on the board, depending on the arrangement of contactors on thejig. It is, in effect, merely a connector between a circuit board or thelike and the circuit testing apparatus. As described in the preferredembodiment, testing is conducted on a wired board having pins; however,it should be apparent that the same principles are equally applicable toa printed circuit board or other element having conductive circuits andany suitable test jig can be employed for interconnecting such a circuitelement with the circuit testing apparatus.

FIG. 2 illustrates a typical wired circuit board having a rectangularmatrix of pins numbered to 19 in the illustrated embodiment. It will, ofcourse, be recognized that a board having only 20 pins in a 4 X 5rectangular matrix is actually extremely simple as compared with thepresently used boards having hundreds or thousands of pins; however, theprinciples are equally applicable to any number of pins, and issufficient for illustrating principles of this invention. The circuitsillustrated on the board of FIG. 2 are also relatively simple, however,they also are sufficient to illustrate principles of this invention.

In a wired circuit board, electrically conductive wires are connectedbetween pins for forming conductive paths prior to installation ofactive circuit components on the board. Thus, in the illustratedembodiment, a wire 22 interconnects pins 0 and 10. Another wire 23interconnects pins 1 and 13. A third wire 24 interconnects pins 2 and 6.Another wire 26 is connected to pins 3, 4, 9 and 14 so that these fourpins are all electrically interconnected. An additional wire 27interconnects pins 5 and 17. Another wire 28 interconnects pins 12 and16, and a final wire 29 interconnects pins 18 and 19.

Each of the pins 0 to 19 comprises a circuit node to which electricalcontact is made by the circuit test jig 21. In a circuit board it mayoccur that not all of the pins are interconnected, and often there willbe pins such as, for example, pins 7 and 8 to which no wire isconnected. As a matter of convenience in nomenclature, the first pin ineach complete circuit when scanned in a particular sequence is referredto as the lowest order node. Thus, for example when scanned in numericalorder, pin 0 is the lowest order node in the circuit including pin 0,wire 22, and pin 10. Likewise, pin 3 is the lowest order node in thecircuit including pins 3, 4, 9 and 14, and wire 26. Although describedherein in terms of lower order nodes, it will become apparent thathigher order nodes could equally well be employed.

In practice of the method provided by this invention, all of the nodeson the circuit board being tested are scanned in a selected sequencewith a forcing voltage. All circuit nodes of a lower order than the nodebeing forced at any instant are electrically interconnected, that is,all are in parallel. The relationship of open circuit or short circuitis determined for each node being forced to all lower order nodescollectively. This identifies all of the lowest order nodes in each ofthe continuous circuits on the board. As pointed out hereinafter thepattern of lowest order nodes is sufficient to distinguish an acceptableboard from an unacceptable one.

In order to practice this portion of the method, a step switch 31, isconnected to the several leads of the circuit test jig 21 so thatelectrical contact can be made by a contactor 32 with each node of thecircuit sequentially. A step latch switch 33 is also connected to theseveral leads of the circuit test jig 21, and as the contactor 32 stepsalong the sequence of circuit nodes latching switches 34 between thecircuit test jig and a common bus 36 are sequentially closed.

Thus, for example, in the illustrative embodiment of FIG. 1, thecontactor 32 of the step switch 31 is in electrical contact with circuitnode 5. The switches 34 connected to the lower order nodes 0 to 4 areall closed so that these lower order nodes are all electricallyinterconnected to the bus 36. The switch 34 associated with the circuitnode 5 and all higher nodes 6 to 19 are open so that these nodes are notconnected to the common bus 36. When the contactor 32 advances insequence to electrical contact with circuit node 6 as illustrated inphantom in FIG. 1, the switch 34 associated with circuit node 5 closes,also as shown in phantom, since circuit node 5 is now a lower order noderelative to node 6.

In the illustrated embodiment, the step switch 31 and step latch switch33 are indicated schematically and may, for example, be rotary stepswitches such as are readily commercially available. When the number ofpins or circuit nodes is high, and it is possible to identify these pinswith a rectangular matrix such as the 4 X 5 array of FIG. 2, it ispreferred to employ conventional crossbar switches as the step switch 31and step latch switch 33. Reed-type crossbar switches are availablehaving switching times in the order of l millisecond in response to an xand y address applied to the switch. This permits sufficiently rapidtesting of large-scale boards with the entire testing sequence asprovided in practice of this invention being completed in only a fewseconds at the very most. If desired, solid state switching instead ofmechanical crossbars switches can be employed for even higher testingrates, which may be desirable if there are several thousand circuitnodes and more than one scan sequence is employed, such as set outhereinafter.

A power supply 37 is connected between the contractor 32 and the commonbus 36 for applying a forcing voltage to the circuit node to which thecontactor is in electrical contact. A resistance 38 between the powersupply 37 and the contactor provides a voltage drop for sensing by acurrent sensor 39. A voltage sensor 41 is also provided between thecontactor 32 and the bus 36 for measuring the voltage thereacross.

The current sensor 39 monitors the leakage current between the contactor32 and the lower order circuit nodes connected to the common bus 36.Preferably, the current sensor is adjustable to provide a logical 0output signal if the insulation or resistance of the circuit is greaterthan an acceptable limit for an open circuit, and a logical 1 if theinsulation is less than the limit acceptable for an open circuit. Thus,if there exists a good conductive path through the tested circuit on thecircuit board being tested, the current sensor provides a 1 outputsignal. The detection limit is adjustable so that a 1 signal is obtainedif there exists a moderate resistance conductive path such as, forexample, might occur through a tiny sliver of metal between intentionalconductors on a printed circuit board.

The voltage sensor 41 monitors the conductivity of the path between thecontactor 32 and the interconnected lower order circuit nodes connectedto the common bus 36. Preferably, the voltage sensor 41 is adjustable toprovide a logical 1 output if the conductivity is sufficiently high foran acceptable circuit path and to provide a logical 0 signal for anunacceptable or open circuit, that is, when there is no electricalcircuit path or a very poor one between the contactor connected node andthe interconnected lower order nodes.

The current sensor 39 and voltage sensor 41 may each merely be aconventional comparator providing a binary digital ouput in response tocomparison of two voltages. It is convenient to provide an adjustablecomparison voltage directly from the power supply 37 so that thesesensors are self compensating.

The output signals from the current sensor 39 and voltage sensor 41 areapplied to analysis logic 42, which, under some conditions, produces arejection signal that is applied directly to fixture control logic 43The analysis logic 42 also produces a circuit status signal that isapplied to an exclusive NOR gate 44. The

analysis logic produces a logical 0 on the signal line to the fixturecontrol logic 43 if either the conductivity or leakage is withinacceptable limits, and produces a logical 1 if both the leakage and theconductivity are acceptable or not acceptable. The analysis logicprovides a logical 1 output if there is an acceptable conductive pathand a logical 0 if the circuit path is open, both of these signals beingapplied as input to the exclusive NOR gate 44.

Within the analysis logic 42 the output signals from both the currentsensor 39 and voltage sensor 41 are applied to an OR gate 46 and to anAND gate 47. The output of the OR gate 46 is in turn applied as an inputto a second AND gate 48. The other input to the second AND gate 48 isthe output of an inerter 49 having as its input the output of the firstAND gate 47. If both the current sensor 39 and voltage sensor 41 havelogical l output, the output of the AND gate 47 is true, or 1, andbecause of the inverter 49, a logical 0 signal is applied to the secondAND gate 48. The output of that gate is, therefore, also a 0 forapplication to the fixture control logic 43. Such signals are obtainedfrom the current sensor and voltage sensor when there is a closedcircuit from the node being forced to the interconnected nodes. If boththe current sensor 39 and voltage sensor 41 have 0 outputs, as is thecase when there is an open circuit, the output of the OR gate 46 isfalse, and hence the output of the second AND gate 48 is also false or0. On the other hand, if either the current sensor 39 or voltage sensor41 has a logical 1 output and the other has a logical 0 output, as canbe the case if there is a high resistance short or a poor contact, forexample, the output of the OR gate 46 is true and the first AND gate 47is false. Because of the inverter 49, the two inputs to the second ANDgate 48 are true, thereby producing a true or logical 1 signal at itsoutput for application to the fixture control logic 43.

It should be noted that the simultaneous checking of conductivity andinsulation of a possible conductive path is also useful in the priortesting technique wherein each node is contacted and a search made forall nodes connected thereto. This provides sensing of high resistancepaths between nodes which are either too low to represent satisfactoryinsulation or too high to represent a satisfactory conductor. When sucha path is found, no matter what scan is employed, the board can besummarily rejected or remedial action taken.

As pointed out hereinabove, when both the current sensor 39 and voltagesensor 41 have true outputs indicating a closed circuit, the output ofthe first AND gate 47 is also true or 1, and this signal is applied tothe exclusive NOR gate 44. In any other case, the ouput of the first ANDgate 47 is false and 0 for application to the exclusive NOR gate. Theoutput of the exclusive NOR gate 44 is applied to a conventional six bitshift register 51. The signal in the sixth or last bit of the shiftregister 51 is also applied to the exclusive NOR gate 44 to form acyclic shift register. it might be noted that either an exclusive NORgate or an exclusive OR gate can be employed in a properly designedcyclic shift register. The output of the exclusive NOR gate 44, andhence the input to the shift register 51, is 1 if both inputs theretoare either 1 or 0. If the two inputs to the exclusive NOR gate are l and0, or 0 and l, the NOR gate output is 0.

A sequence controller 52 provides a reset signal to the shift register51 so that at the beginning of a test cycle, the shift register isfilled with 0's. The sequence control also provides a shift signal tothe shift register for proper timing of the shift in correlation withthe incoming train of signals from the analysis logic 42. The resetsignal is also applied to a step switch control 53 and a step latchswitch control 54. The sequence control also applies a step signal tothe two stepping switch controls 53 and 54 for timing the stepping ofthe switches 31 and 33. The step switch control 53 and step latch switchcontrol 54 provide signals for sequentially stepping the two switches,or if crossbar switches are employed, the switch controls 53 and 54provide at and y address signals.

Input switches 56, which in the illustrated embodiment are merely manualswitches, provide six inputs to a conventional comparator 57. Anothersix inputs to the comparator 57 come from the six bits of the shiftregister 51. The comparator provides a logical 0 output signal when thesix bit binary number or word" in the shift register is identical to thebinary number or word recorded in the input switches 56, and provides alogical 1 output signal when there is any difference between the wordsin the shift register and input switches. Preferably, the input switches56, in the illustrated embodiment, are a pair of manual switches havingthree bit binary outputs and calibrated at the input in an octal codefrom 0 to 7. It is found that an octal code'of but two digits is morereadily understood by an operator than a six ,bit binary code, and itis, therefore, a convenient input arrangement. It should also beapparent that a shift register considerably longer than six bits may beemployed, if desired, thereby calling for more that two octal inputswitches. It will also be apparent that other input switchingarrangements can be employed, either manually or automatically, ifdesired.

The output of the comparator 57 is applied by'way of a NOR gate 58 to apair of final AND gates 59 and 60. The other input to the NOR gate 53 isthe output of an AND gate 61 having as one of its inputs the rejectionor acceptance signal from the final AND gate 48 in the analysis logic42. The other input to the AND gate 61 is a valid time signal from thesequence control 52 having a 1 input when the circuit condition is to betested, and a 0 signal when the circuit condition should not be tested,such as, for example, during the interval that the step switches arestepping. This merely serves as a gate to bar spurious signals.

The other input to the final AND gate 59 is an end test signal from thesequence control 52 which indicates that the circuit testing sequencehas been completed, and when both the end of test signal and NOR gateoutput are true, a logical l or G signal is provided on the output line,indicating that the circuit board under test is acceptable. The outputof the NOR cepted or rejected, or if preferred automatic sorting gat 58is applied t th fi a N ga 6 h g an equipment can be employed fordirecting acceptable inverter 55. The other AND gate input is the end oftest b d t m location and unacceptable boards to a sequence signal. Whenthe NOR gate output is a logical. diff t l ation, 1, the inverterassures that the AND gate output is OPERATION fig; when h NOR gateoutput false or the final The scanning sequence employed across thecircuit gate 60 is true and a NO GO signal appears on the output lineindicating that the circuit board under test be fume val-led however forpurposes of exshould be re-ected position, it Will be assumed in a firstexample that the .l i scan commences at circuit node 0 and continues se-It will be recalled that a logical l re ection signal 5 quentially inincreasing numerical order. In the first from the analysis logic 42 canappear at the AND gate step the contactor is at node 0 and all theswitches 34 61 at any node as they are sequentially scanned. The areopen so that there is always a logical 0 output from GO and NO GOsignals from the final AND gates 59 the analysis logic to the input ofthe NOR gate 44. In and 60 are provided, however, only at the end of thethe second position, the contactor 32 is in contact with completetesting sequence. It is, therefore, in this arcircuit node 1, and theappropriate switch 34 is closed rangement, necessary to store any rejectsignal occurso that circuit node 0 is connected to the common bus ringduring the sequence until the end of the cycle. A 36. In the circuitboard illustrated in FIG. 2, there is no flip-flop 62 is, therefore,provided connected to the electrical connection between pins 0 and land, thereoutput of the AND gate 61 so that the flip-flop is set iffore, a logical 0 is produced by the analysis logic 42 as a rejectsignal should occur at any valid time during the hereinabove described.At the next step, the contactor scanning sequence. Thus, at the end ofthe test, if there 32 (FIG. 1) is in contact with circuit node 2, andthe has been a rejection signal from the analysis logic 42, switchescorresponding to circuit nodes 0 and l are there is a logical l storedin the flip-flop 62 which is apclosed, thereby electricallyinterconnecting these lower plied as an input to the NOR gate 58. If areject signal order circuit nodes. or 1 appears on either the flip-flop62 or the compara- The following table sets forth the logical data obtor57 output at the end of the test, the output of the tained during a scansequence of the board of FIG. 2 NOR gate 58 is 0 and a NO GO signal isprovided at the and gther boards illustrated hereafter:

T A B L E Fig./ Scan NODE Q12345678910111213141516171819 2/A RawData00001010011001101101 2/A SixthBit o0ooo01 111o11oo1oo0o 2/ARegisterlnput 11110110010000 Q Q Q 1. Q 2/A Octal Code 02 3/A RawData00001010011009101101 S/A SixthBit 00000011110110010001 3/A Registerlnput1111011o010oo1g9 9 1 3/A Octal Code 03 4/A RawData 000010100110l11011'014/A SixthBit 00000011110110010010 41A Register-Inputllllotlootootogggggg 4/A Octal Code 00 S/A RawData O0001010011001Q011 QS/A SixthBit 00000011110110010000 5/A Registerlnput 11110110010000 9 QQQ 1 5/ Octal Code 41 output. In the illustrated embodiment, the outputlines merely provide an output signal, and it will be apparent that manyuses can be made of such a signal, such as, indicating to an operatorthat the board should be ac- MA MA 6/A 6M FigJ Scan Raw Data Sixth BitRegister Input NODE Raw Data Sixth Bit Register Input Raw Data Sixth BitRegister Input NODE Raw Data Sixth Bit Register Input NODE Raw DataSixth Bit Register Input Raw Data Fifth Bit Register Input Raw DataFifth Bit Register Input 1 1 O O 1 1 0 1 1 O 1 1 O 1 1 O 0 1 0 O 0 0222212 Octal Code 02 0 O 0 1 O 1 1 1 1 0 O 0 0 1 0 1 1 1 1 1 0 0 0 0 1 01 1 Q Q 1 Q l J Octal Code 13 1 1 1 0 0 0 0 1 0 1 1 Q Q 1 Q l 1 OctalCode 13 1 1 O 0 0 0 1 1 1 1 Q l 1 1 1 1 Octal Code 37 0 1 O 1 Q 0 1 1 00 1 O 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 O 1 0 0 1 1 0 1 0 1 0 1 l 1Q 1 Q Octa1 Code 72 0 1 0 0 Q 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 O 0 00 0 0 0 1 1 0 0 0 O O 0 0 Q Q Q Q 1 Q Octa1 Code 02 O 1 0 0 1 1 O O 1 1O 1 1 0 1 1 1 1 1 0 0 1 O O 0 0 O 1 0 0 0 1 0 0 0 0 0 1 O Q 1 Q l; 1 QOctal Code 26 0 1 0 0 Q 1 O 0 1 1 1 1 1 0 1 1 1 1 1 0 O 1 0 0 1 0 0 1 O1 0 1 O 0 1 0 O 1 0 1 Q Q 1 1 l Octa1 Code 47 In this table, the columnheadings labeled Node indicate the node with which the contactor 32 isconnected at each step in the sequence. The first line in each setlabeled Raw Data indicates the output of the analysis logic 42 to theexclusive NOR gate 44 at each step in the scanning sequence, it beingrecalled that a in the Raw Data indicates an open circuit and a 1indicates a closed circuit. The sets of data in the Table are numberedin correlation with the Figure number the scans represent.

As the contactor 32 (FIG. 1) scans the circuit nodes of the circuitboard illustrated in FIG. 2 there is no electrical interconnectionbetween nodes 0, l, 2, and 3, and, therefore, logical Os are recorded inthe Raw Data line of the Table at each of these points. Thus, forexample, when the contactor 32 is at circuit node 3, circuit nodes 0, l,and 2 are all connected to the common bus 36; however, there is still noconductive path, and there is a 0 entered in the Table.

When the contactor is at circuit node 4, the switch 34 for circuit node3 is closed, and there is now a conductive path from the contactor 32through circuit node 4, the wire 26, and circuit node 3 to the commonbus 36. There is, therefore, a logical 1 signal applied to the exclusiveNOR gate 44 as indicated by the l at node 4 in the Raw Data line of theTable. When the contactor proceeds to node 5, the lower order circuitnodes 0, l, 2, 3, and 4 are all connected to the common bus 36; however,there is no closed circuit between the circuit node 5 and any of thelower order nodes, and, therefore, a logical 0 is entered in the RawData line of the Table. When the contactor is in electrical contact withcircuit node 6, all the lower order nodes 0, I, 2, 3, 4, and S areconnected to the common bus 36. In this circumstance, there is anelectrical connection betweenv the circuit node 6 and the common bus 36by way of the wire 24 to pin 2, and, therefore, a logical l appears inthe first Raw Data line of the Table. As scanning proceeds, the switches34 associated with successive circuit nodes are closed, and logical 0sand Is are provided sequentially to the exclusive NOR gate 44 in apattern indicated as Raw Data.

Initially, the shift register 51 has all six bits filled with 0s, andthe sixth bit is applied as an input to the exclusive NOR gate 44. Atcircuit node 0, the Raw Data is 0, and the sixth bit in the register is0, and, therefore, the output of the exclusive NOR gate is a l, which isentered in the first bit of the shift register (it will be recalled thatthe output of the exclusive NOR gate 44 is a logical 1 if the input bitsare alike, and a logical 0 if the input bits are different). Thus, asseen in the scan of FIG. 2 in the Table, the first six bits of Raw Dataare 000010, and the NOR gate output or register input is l l 1 WI.

When the contactor is at circuit node 6, there is a closed circuit asindicated by the l in the Raw Data line. By this time the first bitinserted into the shift register, a 1, has been shifted to the sixthplace in the register and is applied to the exclusive NOR gate 44 at thesame time as the Raw Data signal. Since these two signals in thisexample are the same, a l is entered in the register as indicated in theRegister Input for the number 6 node in the Table. The Register Input atnode No. 6 is, therefore, a composite of the raw data from node 0 andnode 6. Similarly, when node 7 is tested, an open circuit is found asindicated by the 0 in the Raw Data line. The last bit from the shiftregister now corresponds to the second bit inserted, that is, from node1, and is a logical I. Since the Raw Data signal and Sixth Bit signalare different, a logical 0 is the NOR gate output and register input.

This cyclic shift of the contents of the register from the last bit tothe first bit is continued as the scan proceeds with the composite ofinputs accumulating until the effect of all the raw data is included inthe shift register. Thus, for example, at node 12, the final bit of theregister is a composite of the raw data at circuit node 0 and circuitnode 6, and, therefore, the register input is a composite of the rawdata at circuit nodes 0, 6, and 12. By continually cycling the data inthe cyclic shift register, the six bits recorded therein at the end ofan entire sequence is influenced by all the preceeding bits of raw data.If the scan is repeated, the final recorded data in the register will beidentical each time. Thus, in the six bit register employed in theillustrative embodiment, at the end of a complete scan sequence there isa six bit binary word in the six places of the register, as indicated bythe six underlined bits at the end of the register input line. Asmentioned hereinabove, it is convenient to convert these six bits to twonumerals in an octal code for operator convenience. The octal numberrepresentative of the circuit pattern illustrated in FIG. 2 is 02.

Since the word in the shift register at the end of the scan sequence isthe same if the sequence is repeated, it follows that if a binary wordor its octal equivalent is found for an acceptable circuit board,another acceptable circuit board tested in the same sequence will havethe same code word and may be acceptable. It also turns out that ifthere is a single error in a board, either a short circuit or opencircuit, a different word is invariably contained in the shift registerat the end of the scan sequence, and such a board can be rejected.

FIG. 3 illustrates a printed circuit board having the same wiringconnection as the board illustrated in FIG. 2 except that wire 23between circuit nodes 1 and 13 is broken at point 63, thereby producingan inadvertent open circuit where there should be a circuit. A scan ofthe circuit nodes sequentially in increasing numerical order with alllower order circuit nodes electrically interconnected to the common bus36 (FIG. 1) produces a train of raw data as indicated at raw data line3/A. Up through circuit node 12, the raw data is the same as in the scanof the board illustrated in FIG. 2 since the connections from each nodein sequence to lower order nodes are all the same. When circuit node 13is scanned on the board illustrated in FIG. 3, there is no connectionbetween node 13 and the lower order interconnected nodes 0 through 12and, therefore, a logical 0 appears in the Raw Data for this scaninstead of the logical 1 that appeared when the circuit board of FIG. 2was scanned. (In each instance in the Table the bit that is differentfrom the corresponding bit in the scan with which it is compared isunderlined.) The presence of a logical 0 instead of a logical 1 causes aI rather than a 0 to be entered in the shift register at this point.This bit is carried through the shift register and is combined with theraw data for circuit node 19 which is a logical l in the Raw Data lineso that a logical l is entered in the shift register instead of thelogical 0 entered when the board illustrated in FIG. 2 was scanned. Thefinal six bit word in the register is equivalent to 03 in octal codewhich is different from the 02 found for the acceptable board not havingan open circuit. Since the octal number is different, the boardillustrated in FIG. 3 is found to be different from the boardillustrated in FIG. 2 and can therefore be considered to beunacceptable.

In operation of the apparatus illustrated in FIG. 1 the manual switches56 are set to the octal number 02 when a circuit board is to be tested.When the acceptable board illustrated in FIG. 2is tested according tothe sequential scan, the six bits in the shift register are identical tothe six bit code corresponding to the octal number 02, and the board isaccepted. When the defective board illustrated in FIG. 3 is tested, thesix bit binary word in the register is different from the manual switchsetting and therefore the board is rejected.

FIG. 4 illustrates a circuit board wired like that in FIG. 2 except thatwires 27 and 28 are shorted together at point 64 where they cross. Asequential scan of the nodes of the board illustrated in FIG. 4 yields asequence' of Raw Data as set forth in scan 4/A of the Table. This stringof data is different from the scan obtained from the board illustratedin FIG. 2 by the presence of an extra closed circuit as indicated by thelogical 1 corresponding to circuit node 12 which is nowshorted to lowerorder node by wires 28 and 27, whereas it was previously open to alllower order nodes. This information is cycled through the cyclic shiftregister in the same manner and the resultant octal number at the end ofthe entire scan sequence is 00, which is different from the octal number02 resulting from a scan of the acceptable board of FIG. 2 and,therefore, the board illustrated in FIG. 4 is rejected.

FIG. 5 illustrates another possible fault that may occur in a circuitboard, particularly a wired board. In the board illustrated in FIG. 5the connections of the wires 26 and 29 are interchanged so that wire 26instead of being connected to circuit pin 14 is connected to pin 19, andwire 29 instead of interconnecting pins 18 and 19, interconnects pins 18and 14. The Raw Data scan S/A in the Table shows the sequence of openand closed circuits found as each node is scanned sequentially with alllower order nodes interconnected. Because of the interchangedconnections, the Raw Data for circuit nodes 14, 18 and 19 are changed,thereby effecting a change in the six bit word stored in the register atthe end of the scanned sequence. This word corresponds to an octalnumber 41 which is different from the octal number 02 corresponding tothe acceptable board illustrated in FIG. 2 and, therefore, the boardillustrated in FIG. 5 can be rejected.

It turns out that if there is a single fault, and only a single fault,on a circuit board, the described technique and apparatus willinvariably produce an octal number different from the octal numberrepresenting an acceptable board. There are circumstances, however,where a double fault may occur in a board in such a manner or locationthat the effect of the one fault ex actly compensates for the effect ofthe other fault due to either an equivalent electrical interconnectionon the board or due to the technique of accumulating the raw data in thecyclic shift register.

FIG. 6 illustrates a double fault that causes no change in the Raw Dataof the scan as compared with FIG. 2 since the lowest order node in eachcomplete circuit on the board is not changed. Thus, as illustrated inFIG. 6 wire 23 is connected between pins 2 and 13 instead of between 1and 13 as in the board of FIG. 2, and wire 24 is connected between pins1 and 6 instead of between pins 2 and 6 in the acceptable board. Such apair of faults occurs if the wires leading to pins 1 and 2 areinterchanged. Upon scanning the board illustrated in FIG. 6 inincreasing numerical order, the train of Raw Data signals, as indicatedin scan 6/A of the Table, is unchanged from that found in a scan of theboard illustrated in FIG. 2. If, for example, the contactor 32 (FIG. 1)is at circuit node 6 all lower order nodes 0 through 5 areinterconnected and the apparatus does not distinguish whether wire 24 isconnected to pin 1 or pin 2. The end result is that the binary word inthe shift register at the end of the scan sequence is the same as it isfor the acceptable board of FIG. 2, and the apparatus does notdistinguish the good board from the bad board,

One way of distinguishing a double circuit fault is to reverse the orderof scan starting at the highest numerical pin and scanning in lowernumerical order with the lower order interconnected circuit nodesactually being higher numerical value pins on the board. The dataobtained from such a reverse scan of the boards of FIGS. 2 and 6 are setforth as 2/B and 6/3 in the Table, and because of the nature of theparticular double fault illustrated, both of these scans yield an octalnumber 13. Thus, although in most instances a reverse scan will detectdouble faults, there is still a possibility that in a specialcircumstance as illustrated in the board of FIG. 6, a double fault maystill not be detected. In actual practice, however, the possibility of adouble fault not being identified in a forward scan followed by areverse scan is very low, and such a pair of scans will detect almostall potential faults.

In order to detect a double fault that does not show up in a forwardscan and a reverse scan, a third type of scan can be employed, such asthat set forth in scans 2/C and 6/C in the Table. In this instance, thescan sequence commences in the first column of pins 0, 5, 10, 15, thenproceeds down the second column 1, 6, 11, 16 and so one across the board(such a column by column scan pattern is particularly well suited tocrossbar switching). The scan as set forth at 2/C scanning down eachcolumn successively on the circuit board illustrated in FIG. 2 resultsin a six bit word in the shift register equivalent to an octal number37. When the same scan is conducted on the circuit board illustrated inFIG. 6 having a double fault, the sequence of Raw Data set forth in scan6/C in the Table results with three differences appearing in the RawData as indicated by the underlined bits. The result is a final binaryword in the register having an octal equivalent of 72, different fromthe 37 found in the scan of the board illustrated in FIG. 2. Thus,although certain double faults can go undetected with certain orders ofscan, there is some order of scan of the board that will always disclosethe faults. Although the probability of a double fault being undetectedis low when two scans are conducted with different scan sequences, itmay be desirable in some circumstances to conduct three or more scanswith different scan sequences so that plural faults on a board can bedetected at a stage prior to installation of components. Because of thevery short time required in order to make a single scan of a board, eventhough it has several thousand pins, there is no significant difficultyin conducting a series of scans of different sequences in order toassure that a board is satisfactory. With a technique as provided inpractice of this invention wherein all lower order nodes areelectrically interconnected, several scans can be conducted in a muchshorter time than a single scan by any prior technique.

FIG. 7 illustrates a printed circuit board having circuits thereon wiredin substantially the same manner as the board illustrated ll. FIG. 2;however, a double fault is present on the board illustrated in FIG. 7.Thus, wire 23 interconnecting pins and is also shorted to pin 15. Theother fault on this board is in wire 26 which is not connected to pin 9,as it should be, yielding an open circuit. Assuming a forward scan ofthis board in order of increasing numerical value of the pins, asequence of data as set forth in scan 7/A is produced. In this scan, theraw data is different from that of the similar scan 2/A for the boardillustrated in FIG. 2 at the underlined Raw Data points in the Tablecorresponding to circuit node 9 and circuit node 15. Because these twodifferences are six nodes apart and the data is summarized in a cyclicshift register having six bits, the two faults exactly compensate. It isof no significance that one fault is a short circuit and the other is anopen circuit. It is only of significance that the two faults are spacedapart in the scan pattern the length of the shift register or somemultiple thereof. It will be noted that the final six bit word in theregister input for this scan has an octal number equivalent of 02,exactly the same as the octal number for the satisfactory boardillustrated in FIG. 2.

If the length of the shift register is n bits and two faults occur,which are n or multiple of n apart in the scan sequence, then the pairof faults will not be detected. This situation could be detected by anorder of scan different from the reverse, for example, a row by rowscan. It should be noted that with a six bit register, the probabilityof a pair of faults compensating is higher than if a longer shiftregister is employed. In an actual apparatus as distinguished from theexemplary embodiment illustrated, the cyclic shift register ispreferably 15, I8, or 21 bits long. Multiples of three are preferredonly to provide convenience in octal coding of manual input switches.

The two faults spaced apart by the length of the shift register are alsodetected if the length of the register is different. Thus, for example,if instead of recycling the sixth bit of a six bit shift register, thefifth bit is recycled, the cyclic register is in effect five bits long.When the circuit board illustrated in FIG. 2 is scanned with a five bitregister, a sequence of binary bits as set forth in scan 2/D of theTable is produced, and the final six bit word in the register has anoctal equivalent of 26. The Raw Data input is unchanged. When the boardillustrated in FIG. 7 is scanned with the data recorded in a five bitcyclic shift register, a sequence of data as set forth in scan 7/8 inthe Table is produced. In this case, the Raw Data has two differencesfrom the Raw Data of the scan of the acceptable board illustrated inFIG. 2, but these two differences no longer compensate and there is afinal word in the six bit shift register having an octal equivalent of47, different from the octal number 26 of the good board of FIG. 2.

Rather than employ two scans with cyclic shift registers of differentlengths, the data can be applied simultaneously to two shift registersof different length, such as, for example, one of five bits and one ofsix bits. The only time double faults could compensate would then be ina situation where they were spaced apart in a scan sequence by adistance equal to the product of the lengths of the two registers.

A somewhat similar effect can be achieved with a single shift registerin an arrangement as illustrated in FIG. 8. As illustrated in thisembodiment, which comprises a cyclic shift register which can be readilysubstituted for the shift register in the embodiment of FIG. 1, raw datasuch as from the analysis logic 42 of FIG. 1 is applied to an exclusiveNOR gate 66. The output of the NOR gate 66 is applied as an input to asix bit shift register 67. The sixth bit of the shift register 67 isapplied as one input to an exclusive NOR gate 68, and the contents ofthe fifth bit of the shift register is applied as the other input to theNOR gate. The output of the exclusive NOR gate 68 is cycled back to theinput of the initial exclusive NOR gate 66. In this manner, the outputof the exclusive NOR gate 68 is a composite of the data accumulated inthe fifth and sixth bits, and this data is recycled to the inputexclusive NOR gate 66 for combination with the raw data.

Although this arrangement increases the number of possibilities ofcompensating faults (e.g., adjacent faults can eompensate), it alsoeffectively increases the length of the shift register at a faster rate,thereby reducing the overall probability of a pair of faults goingundetected. The probability can be further lowered by additionalrecycling of, for example, the fourth and sixth bits of the shiftregister through an exclusive NOR gate connected serially with theexclusive NOR gate 68. Many other similar arrangements can be devised byone skilled in the art.

It should be noted in application of the described technique accordingto the illustrated embodiment, that the presence or absence of faults inthe circuit board is detected. The preferred arrangement does notprovide an identification of the location or nature of the fault. Thisis due to the reduction in word length by the cyclic shift register inorder to provide convenience in data input by manual switches. If it isdesired to identify the approximate location of a fault on a circuitboard, a shift register having at least as many bits as there arecircuit nodes on the board can be employed, and the location of the databit having a difference from an acceptable board can be identified. Ifthis does not exactly pinpoint the fault, it at least significantlyreduces the possible places for the fault to exist and manual techniquesor other automatic techniques can be used thereafter.

In the illustrative embodiment,.a manual input arrangement is set forthwherein the octal number representative of the data in the shiftregister is known for an acceptable circuit board. The octal number canbe found readily by scanning a board known to be acceptable in thedesired scan pattern or patterns. In this way, very complex circuitconfigurations can be checked out without preparing lengthy computerprograms to work out the desired circuit arrangement. Complex circuitarrangements can be verified without searching for members of eachcircuit string, which vastly reduces the time required for a completecircuit checkout. It is also apparent that the manual input can bedispensed with, and a scan of the acceptable board in the same patterncan be employed directly as the data input to the comparator.

The described method and apparatus is valuable in that it virtuallyeliminates the need for storing large masses of information whichdescribe separate wire lists for the large variety of circuit boards andwired panels employed in electronic apparatus. Instead, a relatively fewcheck digits in the form of numbers only a few bits long for each typecircuit board provides a reasonable probability of detecting those shortcircuits or open circuits which would make one circuit board connectionpattern different from a previously tested acceptable unit or design.This apparatus and method makes it practical to test 100 percent of alarge number of printed circuit boards or wired boards before activecomponents are mounted and soldered. Prior art testers are expensive andtake too long to select from a memory the proper testing pattern and runthe test for all possible circuit combinations. As a result, it has beenthe practice to test only connections to theedge tabs of a board andcomponents have often been assembled on defective boards with scrappingor rework of the boards being required when functional tests areperformed. With the described method and apparatus, the boards can becompletely checked before any components are mounted thereon, therebyyielding substantial economies in manufacturing costs.

Although limited embodiments of apparatus constructed according toprinciples of this invention has been described and illustrated herein,many modifications and variations will be apparent to one skilled in theart. Thus, for example, the analysis and rejection control logic can besubstantially different from that illustrated in the exemplaryembodiment and other means for forming a composite of data of limitedword length can be provided.

Although in the preferred embodiment, as the step switch scans along thecircuit nodes successively all lower order circuit nodes areinterconnected, it will be appreciated that the reverse can be employedequally well, it being only a matter of nomenclature as to what isconsidered a lower order node. Thus, as the scan starts all lower ordernodes can be interconnected, and as the scan proceeds sequentially alongthe circuit nodes the lower order nodes are successively'disconnected.It will therefore be understood that lower order nodes and lowest ordernode are merely convenient nomenclature and higher order and highestorder could equally well be employed. Many other modifications andvariations will be apparent and it is, therefore, to be understood thatwithin the scope of the appended claims the invention may be practicedotherwise than as specifically described.

What is claimed is:

1. In a circuit testing apparatus for testing a circuit arrangementhaving a plurality of circuit nodes comprising means for applying a testsignal to a circuit node, means for electrically interconnecting allcircuit nodes of lower order than the circuit node to which the signalis applied at each instant, means for sensing the presence or absence ofthe test signal on the interconnected nodes, and means for storingindicia of said presence or absence, an improved scanning cycle meanscomprising:

means for applying the test signal successively without interruption toeach circuit node of the plurality of circuit nodes regardless of thepresence or absence of the test signal on the interconnected nodes.

2. Circuit testing apparatus for testing a circuit arrangement having aplurality of circuit nodes comprising:

means for applying a forcing voltage to each circuit node successivelywithout interruption;

means for electrically interconnecting all circuit nodes of lower orderthan the circuit node to which the voltage is applied at each instant;

voltage sensing means for sensing the presence or absence of aconductive path between the test circuit node and the interconnectedcircuit nodes having a greater conductivity than a preselected value;

current sensing means for sensing the presence or absence of a currentpath between the test circuit node and the interconnected circuit nodeshaving a conductivity greater than a preselected value; and

means for generating a rejection signal if both the voltage sensingmeans and current sensing means indicate a conductive path inside oroutside of acceptable limits and for generating an acceptance signal ifonly one of either the voltage sensing means or current sensing meansindicates a conductive path within acceptable limits.

3. A circuit testing apparatus as defined in claim 2 further comprising:

means for producing a first logical signal representative of aconductive path between the test circuit node and the interconnectedcircuit nodes and a second logical signal representative of absence of aconductive path therebetween;

a cyclic shift register connected to the means for producing logicalsignals for generating a number at the end of a testing sequence whereinall circuit nodes are successively tested, the number having fewer bitsthan the number of circuit nodes tested;

means for inserting into the apparatus a number representative of acircuit having selected interconnections; and

means for comparing the inserted number with the number recorded in theshift register at the end of a testing sequence and for producing acomparison signal indicative of identity or lack of identity of thenumbers.

4. A circuit testing apparatus as defined in claim 3 further comprising:

means for generating a rejection signal if both the voltage sensingmeans and current sensing means indicate a conductive path inside oroutside of ac ceptable limits, and for generating an acceptance signalif only one of either the voltage sensing means or current sensing meansindicates a conductive path within acceptable limits; and

means for combining the rejection signal and acceptance signal with thecomparison signal for accepting or rejecting a circuit.

5. A circuit testing apparatus as defined in Claim 4 wherein the meansfor applying a test signal to each circuit node successively comprises astep switch; and wherein the means for electrically interconnecting allcircuit nodes of lower order comprises a step latch switch.

6. Circuit testing apparatus for testing a circuit arrangement having aplurality of circuit nodes comprising:

means for applying a test signal to each circuit node successivelywithout interruption;

means for electrically interconnecting all circuit nodes of lower orderthan the circuit node to which the signal is applied at each instant;

means for generating a first logical signal representative of a closedcircuit between the circuit node being tested and the interconnectedlower order circuit nodes and a second logical signal representative ofan open circuit therebetween; and

means for comparing a logical word formed of a sequence of first andsecond logical signals produced by the means for generating with asecond logical word representative of a circuit having selectedinterconnections.

7. A circuit testing apparatus as defined in claim 6 further comprising:

means for reducing the sequence of signals to a number having fewer bitsthan the number of circuit nodes tested.

8. Circuit testing apparatus for testing a circuit having a plurality ofnodes comprising:

means for selectively interconnecting circuit nodes for dividing aplurality of circuit nodes into a first set of externally connectednodes and a second set of externally non-connected nodes;

means for generating a test signal;

means for applying the test signal to each circuit node in the secondset successively without interruption over substantially the entireplurality of circuit nodes and in coordination therewith increasing byone the number of nodes in one set and decreasing by one the nodes inthe other set;

means for sensing the presence of absence of the signal on the first setof externally connected nodes; and

means for generating a signal indicative thereof.

9. Circuit testing apparatus as defined in claim 8 wherein the means forsuccessively scanning comprises means for transferring the node justtested from the second set to the first set until all nodes except afinal test node are interconnected.

10. Circuit testing apparatus as defined in claim 9 wherein the meansfor sensing a signal comprises:

a voltage sensor for sensing the presence or absence of a voltage ofselected magnitude between the test node and the first set of externallyconnected nodes; and

a current sensor for sensing the presence or absence of a current ofselected magnitude between the test node and the first set of externallyconnected nodes.

11. Circuit testing apparatus as defined in claim 8 further comprising:

means for temporarily recording a history of the signals sensed on thefirst set as a number;

means for generating a number representative of an acceptable circuit;and

means for comparing the recorded number with the generated number.

12. A circuit testing apparatus as defined in claim 11 wherein the meansfor temporarily recording comprises a cyclic shift register connected tothe means for sensing.

13. A method of testing a circuit having a plurality of circuit nodescomprising the steps of:

applying a signal to a first circuit node;

interconnecting a plurality of other circuit nodes;

sensing the presence or absence of the signal on the interconnectednodes;

interconnecting the first circuit node with the previouslyinterconnected circuit nodes;

applying a signal to a second circuit node;

sensing the presence or absence of the signal on the new set ofinterconnected nodes; and

sequentially repeating the interconnecting of circuit nodes and applyingof signals over the entire plurality of circuit nodes withoutinterruption regardless of presence or absence of the signal on theinterconnected nodes. 14. A method of testing a circuit as defined inclaim 13 further comprising:

recording a historical sequence of signals sensed on the interconnectednodes; and

comparing the recorded signals with a plurality of signalsrepresentative of an acceptable circuit.

15. A method of testing a circuit as defined in claim 14 wherein therecording step further comprises reducing the sequence of signals to anumber having fewer bits than the number of circuit nodes tested.

16. A method of testing as defined in claim 13 comprising the step of:

repeating the interconnecting of circuit nodes, applying of signals, andsensing the presence or absence of the signal over substantially theentire plurality of circuit nodes in a scan sequence different from thefirst sequence of interconnecting and applying.

17. A method of testing a circuit having a plurality of circuit nodescomprising the steps of:

sequentially sensing the presence or absence of electrical continuitybetween each successive circuit node and all circuit nodes of lowerorder than the first circuit node for distinguishing all lowest ordercircuit nodes in each continuous circuit from all other circuit nodes;and

comparing the location of lowest order circuit nodes so distinguishedwith desired locations of lowest order circuit nodes without searchingfor members of each circuit string.

18. Circuit testing apparatus for a circuit board having a plurality ofcircuit nodes comprising:

means for distinguishing all lowest order circuit nodes in eachcontinuous circuit from all other circuit nodes; and means for comparingthe locations of lowest order circuit nodes so distinguished withdesired locations of lowest order circuit nodes without searching formembers of each circuit string; and wherein the means for identifyingall lowest order nodes comprises means for sequentially sensing thepresence or absence of electrical continuity between each successivecircuit node and all circuit nodes of lower order than each successivecircuit node respectively.

19. A circuit testing apparatus for testing a circuit arrangement havinga plurality of circuit nodes comprismg:

scanning cycle means for applying a test signal successively withoutinterruption to each circuit node of the plurality of circuit nodes;

means for electrically interconnecting all circuit nodes of lower orderthan the circuit node to which the signal is applied at each instant;and

sensor meaps for sensing the presence or absence of the test signal onthe lower order nodes.

20. A method of testing the acceptability of a circuit arrangementhaving a plurality of circuit nodes comprising the steps of:

selecting an arbitrary ordered sequence for all of the circuit nodes;applying a test signal to one of the circuit nodes; electricallyinterconnecting all circuit nodes of lower order than the circuit nodeto which the signal is applied at each instant;

LII

repeating the steps of applying, interconnecting, and

sensing successively with respect to each circuit node in the secondsequence of circuit nodes.

22. A method as defined in claim 21 wherein the second sequence is thereverse of the first sequence.

23. In a method for testing a circuit arrangement having a plurality ofcircuit nodes including the steps of sensing the presence or absence ofa test signal between one circuit node and interconnected circuit nodesof lower order than the one circuit node, and generating a comparisonsignal indicative of the presence or absence, the improvementcomprising:

successively sensing the presence or absence of the test signal betweeneach circuit node and its corresponding interconnected lower order nodesover at least two sequences of circuit nodes that are different fromeach other. 24. In a method for testing as defined in claim 23 thefurther improvement wherein one of the sequences is the reverse of theother sequence.

1. In a circuit testing apparatus for testing a circuit arrangementhaving a plurality of circuit nodes comprising means for applying a testsignal to a circuit node, means for electrically interconnecting allcircuit nodes of lower order than the circuit node to which the signalis applied at each instant, means for sensing the presence or absence ofthe test signal on the interconnected nodes, and means for storingindicia of said presence or absence, an improved scanning cycle meanscomprising: means for applying the test signal successively withoutinterruption to each circuit node of the plurality of circuit nodesregardleSs of the presence or absence of the test signal on theinterconnected nodes.
 2. Circuit testing apparatus for testing a circuitarrangement having a plurality of circuit nodes comprising: means forapplying a forcing voltage to each circuit node successively withoutinterruption; means for electrically interconnecting all circuit nodesof lower order than the circuit node to which the voltage is applied ateach instant; voltage sensing means for sensing the presence or absenceof a conductive path between the test circuit node and theinterconnected circuit nodes having a greater conductivity than apreselected value; current sensing means for sensing the presence orabsence of a current path between the test circuit node and theinterconnected circuit nodes having a conductivity greater than apreselected value; and means for generating a rejection signal if boththe voltage sensing means and current sensing means indicate aconductive path inside or outside of acceptable limits and forgenerating an acceptance signal if only one of either the voltagesensing means or current sensing means indicates a conductive pathwithin acceptable limits.
 3. A circuit testing apparatus as defined inclaim 2 further comprising: means for producing a first logical signalrepresentative of a conductive path between the test circuit node andthe interconnected circuit nodes and a second logical signalrepresentative of absence of a conductive path therebetween; a cyclicshift register connected to the means for producing logical signals forgenerating a number at the end of a testing sequence wherein all circuitnodes are successively tested, the number having fewer bits than thenumber of circuit nodes tested; means for inserting into the apparatus anumber representative of a circuit having selected interconnections; andmeans for comparing the inserted number with the number recorded in theshift register at the end of a testing sequence and for producing acomparison signal indicative of identity or lack of identity of thenumbers.
 4. A circuit testing apparatus as defined in claim 3 furthercomprising: means for generating a rejection signal if both the voltagesensing means and current sensing means indicate a conductive pathinside or outside of acceptable limits, and for generating an acceptancesignal if only one of either the voltage sensing means or currentsensing means indicates a conductive path within acceptable limits; andmeans for combining the rejection signal and acceptance signal with thecomparison signal for accepting or rejecting a circuit.
 5. A circuittesting apparatus as defined in Claim 4 wherein the means for applying atest signal to each circuit node successively comprises a step switch;and wherein the means for electrically interconnecting all circuit nodesof lower order comprises a step latch switch.
 6. Circuit testingapparatus for testing a circuit arrangement having a plurality ofcircuit nodes comprising: means for applying a test signal to eachcircuit node successively without interruption; means for electricallyinterconnecting all circuit nodes of lower order than the circuit nodeto which the signal is applied at each instant; means for generating afirst logical signal representative of a closed circuit between thecircuit node being tested and the interconnected lower order circuitnodes and a second logical signal representative of an open circuittherebetween; and means for comparing a logical word formed of asequence of first and second logical signals produced by the means forgenerating with a second logical word representative of a circuit havingselected interconnections.
 7. A circuit testing apparatus as defined inclaim 6 further comprising: means for reducing the sequence of signalsto a number having fewer bits than the number of circuit nodes tested.8. Circuit testing apparatus for testing a circuit having a plurality ofnodEs comprising: means for selectively interconnecting circuit nodesfor dividing a plurality of circuit nodes into a first set of externallyconnected nodes and a second set of externally non-connected nodes;means for generating a test signal; means for applying the test signalto each circuit node in the second set successively without interruptionover substantially the entire plurality of circuit nodes and incoordination therewith increasing by one the number of nodes in one setand decreasing by one the nodes in the other set; means for sensing thepresence of absence of the signal on the first set of externallyconnected nodes; and means for generating a signal indicative thereof.9. Circuit testing apparatus as defined in claim 8 wherein the means forsuccessively scanning comprises means for transferring the node justtested from the second set to the first set until all nodes except afinal test node are interconnected.
 10. Circuit testing apparatus asdefined in claim 9 wherein the means for sensing a signal comprises: avoltage sensor for sensing the presence or absence of a voltage ofselected magnitude between the test node and the first set of externallyconnected nodes; and a current sensor for sensing the presence orabsence of a current of selected magnitude between the test node and thefirst set of externally connected nodes.
 11. Circuit testing apparatusas defined in claim 8 further comprising: means for temporarilyrecording a history of the signals sensed on the first set as a number;means for generating a number representative of an acceptable circuit;and means for comparing the recorded number with the generated number.12. A circuit testing apparatus as defined in claim 11 wherein the meansfor temporarily recording comprises a cyclic shift register connected tothe means for sensing.
 13. A method of testing a circuit having aplurality of circuit nodes comprising the steps of: applying a signal toa first circuit node; interconnecting a plurality of other circuitnodes; sensing the presence or absence of the signal on theinterconnected nodes; interconnecting the first circuit node with thepreviously interconnected circuit nodes; applying a signal to a secondcircuit node; sensing the presence or absence of the signal on the newset of interconnected nodes; and sequentially repeating theinterconnecting of circuit nodes and applying of signals over the entireplurality of circuit nodes without interruption regardless of presenceor absence of the signal on the interconnected nodes.
 14. A method oftesting a circuit as defined in claim 13 further comprising: recording ahistorical sequence of signals sensed on the interconnected nodes; andcomparing the recorded signals with a plurality of signalsrepresentative of an acceptable circuit.
 15. A method of testing acircuit as defined in claim 14 wherein the recording step furthercomprises reducing the sequence of signals to a number having fewer bitsthan the number of circuit nodes tested.
 16. A method of testing asdefined in claim 13 comprising the step of: repeating theinterconnecting of circuit nodes, applying of signals, and sensing thepresence or absence of the signal over substantially the entireplurality of circuit nodes in a scan sequence different from the firstsequence of interconnecting and applying.
 17. A method of testing acircuit having a plurality of circuit nodes comprising the steps of:sequentially sensing the presence or absence of electrical continuitybetween each successive circuit node and all circuit nodes of lowerorder than the first circuit node for distinguishing all lowest ordercircuit nodes in each continuous circuit from all other circuit nodes;and comparing the location of lowest order circuit nodes sodistinguished with desired locations of lowest order circuit nodeswithout searching for members of each circuit string.
 18. Circuittesting apparatus for a circuit board having a plurality of circuitnodes comprising: means for distinguishing all lowest order circuitnodes in each continuous circuit from all other circuit nodes; and meansfor comparing the locations of lowest order circuit nodes sodistinguished with desired locations of lowest order circuit nodeswithout searching for members of each circuit string; and wherein themeans for identifying all lowest order nodes comprises means forsequentially sensing the presence or absence of electrical continuitybetween each successive circuit node and all circuit nodes of lowerorder than each successive circuit node respectively.
 19. A circuittesting apparatus for testing a circuit arrangement having a pluralityof circuit nodes comprising: scanning cycle means for applying a testsignal successively without interruption to each circuit node of theplurality of circuit nodes; means for electrically interconnecting allcircuit nodes of lower order than the circuit node to which the signalis applied at each instant; and sensor means for sensing the presence orabsence of the test signal on the lower order nodes.
 20. A method oftesting the acceptability of a circuit arrangement having a plurality ofcircuit nodes comprising the steps of: selecting an arbitrary orderedsequence for all of the circuit nodes; applying a test signal to one ofthe circuit nodes; electrically interconnecting all circuit nodes oflower order than the circuit node to which the signal is applied at eachinstant; sensing the presence or absence of the test signal on theinterconnected nodes; and applying the test signal successively withoutinterruption to each circuit node in the sequence of circuit nodes. 21.A method as defined in claim 20 comprising the additional steps of:selecting a second arbitrary ordered sequence for all of the circuitnodes different from the first ordered sequence; and repeating the stepsof applying, interconnecting, and sensing successively with respect toeach circuit node in the second sequence of circuit nodes.
 22. A methodas defined in claim 21 wherein the second sequence is the reverse of thefirst sequence.
 23. In a method for testing a circuit arrangement havinga plurality of circuit nodes including the steps of sensing the presenceor absence of a test signal between one circuit node and interconnectedcircuit nodes of lower order than the one circuit node, and generating acomparison signal indicative of the presence or absence, the improvementcomprising: successively sensing the presence or absence of the testsignal between each circuit node and its corresponding interconnectedlower order nodes over at least two sequences of circuit nodes that aredifferent from each other.
 24. In a method for testing as defined inclaim 23 the further improvement wherein one of the sequences is thereverse of the other sequence.